Architecture-Dependent Loop Scheduling via Communication-Sensitive Remapping

In this paper, we propose a novel efficient technique called cyclo-compaction scheduling, taking into account the data transmission delays and loop carried dependency associated with specific target architectures. This technique uses the retiming technique (loop pipelining), implicitly applied, and a task remapping to appropriate processors in order to compact the schedule length and improve the parallelism iteratively while handling the underlying imposed communication environment and resource constraints. Algorithms and the corresponding theorems are presented. Experimental results for different architectures show the effectiveness of our algorithm.